1. Field of the Invention
The invention relates generally to digital systems. The invention relates more specifically to digital circuits that are to operate in a selected one of plural voltage-signaling modes, e.g., a 3.3V mode or a 5V mode.
2a. Cross Reference to Related Applications
The following copending U.S. patent application(s) is/are assigned to the assignee of the present application, is/are related to the present application and its/their disclosures is/are incorporated herein by reference:
(A) Ser. No. 08/186,050 [Attorney Docket No. AMDI8019] filed concurrently herewith by Chih-Siung Wu et al, and entitled, INTEGRATED SCSI AND ETHERNET CONTROLLER ON A PCI LOCAL BUS; and PA1 (B) Ser. No. 08/184,295 [Attorney Docket No. AMDI8024] filed Jan.21, 1994 by Chih-Siung Wu et al, and entitled, APPARATUS AND METHOD FOR INTEGRATING BUS MASTER OWNERSHIP OF LOCAL BUS LOAD BY PLURAL DATA TRANSCEIVERS. PA1 (A) PCI Local Bus Specification, Revision 2.0, Apr. 30, 1993; available from PCI Special Interest Group, 5200 N.E. Elam Young Parkway, Hillsboro, Oreg. (USA) 97124. PA1 (A) the 5V digital signaling type, wherein a logic low ("0") is to be represented by a voltage level in the range -0.5V to 0.8V and a logic high ("1") is to be represented by a voltage level in the range 2.0V to V.sub.cc +0.5V, V.sub.cc being in the range 4.75 to 5.25V; or PA1 (B) the 3.3V digital signaling type, wherein a logic low ("0") is to be represented by a voltage level in the range -0.5V to 0.325V.sub.cc and a logic high ("1") is to be represented by a voltage level in the range 0.475V.sub.cc to V.sub.cc +0.5V, V.sub.cc being in the range 3.0 to 3.6V.
2b. Cross Reference to Related Other Publications
The following publication(s) is/are believed to be related to the present application and is/are cited here for purposes of reference:
3. Description of the Related Art
The 5 volt DC level has served as a standard power supply value for TTL (Transistor-Transistor Logic) and like digital systems for many years.
Recently, the industry has begun to adopt an alternate, 3.3 volt DC level as a standard for powering high-density, high-speed, integrated circuits. This presents the problem that some designs are expected to operate in a 5V signaling mode, some designs are expected to operate in a 3.3V signaling mode and some designs are expected to operate in a hybrid environment that uses both the 5V and the 3V signaling modes.
An example of the possibility for such multi-mode operation is found in the recently introduced, "PCI local bus" standard. PCI stands for Peripheral Component Interconnect. The standard is specified by the PCI Special Interest Group of Hillsboro, Oreg. (USA). One of the PCI specifications (PCI sections 4.2.1 and 4.2.2) is that digital signals on the PCI local bus can be of either:
To be truly PCI-compliant, an on-bus device has to be capable of operating in either the 5V or 3.3V signaling mode. But a shift from one signaling environment to another (e.g., from 5V to 3.3V) calls for making certain changes in fundamental parameters of input and output circuits. More specifically, the switching threshold of each inverter or other logic gate on a dual-mode bus has to be appropriately reduced when a change is made from a 5V signaling mode to a 3.3V signaling mode. And if an output buffer on the dual-mode bus is to source or sink predefined minimum currents (e.g., 44 mA of pull-up current), the internal pull-up resistance (and/or tie-down resistance, if any) of the buffer has to be appropriately decreased when the change is made from a 5V signaling mode to a 3.3V signaling mode so that the same current levels can be maintained even though the drive voltage is lowered.
It has been proposed that a dedicated, mode-indicating pin should be included on every integrated circuit chip to indicate to the internal circuitry of the chip whether an external bus is of the 5V signaling type or of the 3.3V signaling type. The internal circuitry of the chip would then reconfigure itself in response to such an indication to conform with 5V signaling requirements or 3.3V signaling requirements.
Such an arrangement has the disadvantage of reducing the number of pins available for other functions on an IC package of a fixed pin count. It also adds complexity to the printed circuit board on which one or more such dual-mode chips are mounted because an extra trace has to be routed to the dedicated, 5V/3.3V-indicating pin of each dual mode chip. Circuit manufacturers have to go through the expense of testing this extra circuitry and setting its level to one or the other of opposed levels in order to properly indicate 5V or 3.3V operation.